The disclosed subject matter relates generally to integrated circuit devices and, more particularly, to a circuit for negative bias temperature instability compensation.
Negative Bias Temperature Instability (NBTI) is an issue in deep submicron technologies. NBTI affects devices which are kept in an active state for extended periods of time. For example, a custom array, or any domino circuit, often requires a keeper to hold the voltage on pre-charged bitlines if none of the pull down transistors fire. To be properly sized, the keeper should be large enough to compensate the pull down leakage under worst process corners and noise considerations and should also be small enough to ensure fast evaluation when pull down transistors do fire. However, NBTI effectively weakens the keeper PFET over time. In 40 nm process technology, positive bias temperature instability (PBTI) is not pronounced, and also most of the time, pull down NFETs are in off mode. In contrast, keeper PFETs are almost always stressed. Another example of such a stressed device is a sleep enable circuit that selectively charges a voltage bus during an active state and isolates the bus during a sleep state. In designing integrated circuit device, designers attempt to account for NBTI by adjusting the specifications of the device. Exemplary techniques for mitigating the effects of NBTI involve changing the specifications of the dynamic devices or attempting to compensate for the degradation.
Changing the specifications may include reducing the number of pull-down devices on the array bitlines (i.e., or the dynamic node in a generic domino logic circuit) such that required keeper size can be more readily met. This approach sacrifices design density, and is thus infeasible in large arrays. Oversizing the keeper to account for future degradation results in a performance penalty by increasing the pull-down speed.
A compensation approach involves periodically adjusting the body bias of the n-well where the keeper is formed. Such an approach is typically based upon a generic degradation circuit and applies a global body bias to all PFETs in the n-well. Applying forward bias to many large n-wells creates more leakage by slightly forward biasing the diodes. Also, the general bias is not specific to the actual keeper strength, resulting in the risk of over-compensating and slowing down a critical path as a result. Because the amount of forward bias is bounded by the diode onset voltage, the degree of compensation is limited. Finally, creating extra well-ties in dense arrays can consume significant circuit area.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.